1. Field of the Invention
Embodiments of the invention generally relate to a processing platform for conducting an electroless deposition process.
2. Description of the Related Art
Metallization of sub 100 nanometer sized features is a foundational technology for present and future generations of integrated circuit manufacturing processes. More particularly, in devices such as ultra large scale integration-type devices, i.e., devices having integrated circuits with more than a million logic gates, the multilevel interconnects that lie at the heart of these devices are generally formed by filling high aspect ratio, i.e., greater than about 10:1, interconnect features with a conductive material, such as copper. Conventionally, deposition techniques such as chemical vapor deposition and physical vapor deposition have been used to fill interconnect features. However, as the interconnect sizes decrease and aspect ratios increase, void-free interconnect fill via conventional metallization techniques becomes increasingly difficult. As a result, plating techniques, i.e., electrochemical plating and electroless deposition, have emerged as promising processes for void free filling of sub 100 nanometer sized high aspect ratio interconnect features in integrated circuit manufacturing processes. Further, plating processes, and in particular, electroless deposition processes have emerged as promising processes for depositing post deposition layers, such as capping layers.
However, with regard to electroless deposition processes, conventional processing apparatuses and methods have faced challenges in accurately controlling the electroless deposition process and the defect ratios in the resulting deposition layers. Further, a functional integrated platform for an electroless deposition process capable of pre and post deposition cleaning of substrates, depositing uniform electroless layers with minimal defects, and annealing the substrates is needed.